MRAM devices have been widely used as non-volatile memory devices, which can be operated at a low voltage and/or a high speed. In a unit cell of the MRAM devices, one bit of data is stored in a Magnetic Tunnel Junction (MTJ) of a magnetic resistor. The MTJ generally includes first and second ferromagnetic layers and a tunneling insulation layer interposed between the first and second ferromagnetic layers. Magnetic polarization of the first ferromagnetic layer, which is also referred to as a free layer, can be changed by a magnetic field that crosses the MTJ. The magnetic field can be induced by a current that flows around the MTJ. The magnetic polarization of the free layer may be parallel or anti-parallel to the magnetic polarization of the second ferromagnetic layer, also referred to as a pinned layer. Current for generating the magnetic field passes through a conductive layer, which is referred to as a digit line.
According to spintronics based on quantum mechanics, in the event that magnetic spins in the free layer and the pinned layer are arrayed to be parallel to each other, a tunneling current passing through the MTJ exhibits a maximum value. On the other hand, in the event that the magnetic spins in the free layer and the pinned layer are arrayed to be anti-parallel to each other, the tunneling current passing through the MTJ has a minimum value. Thus, data of the MRAM cell can be determined according to the direction of the magnetic spins in the free layer.
FIG. 1 is a cross-sectional view illustrating a conventional MRAM cell.
Referring to FIG. 1, a first interlayer insulating layer 3 is formed on a semiconductor substrate 1. A digit line 5 is disposed on the first interlayer insulating layer 3. The digit line 5 and the first interlayer insulating layer 3 are covered with a second interlayer insulating layer 7. A magnetic resistor 16 is disposed on the second interlayer insulating layer 7 to overlap with a predetermined region of the digit line 5. The magnetic resistor 16 includes a lower electrode 11, an MTJ 13 and an upper electrode 15 which are sequentially stacked. The magnetic resistor 16 and the second interlayer insulating layer 7 are covered with a third interlayer insulating layer 17. A bit line 19, electrically connected to the upper electrode 15, is disposed on the third interlayer insulating layer 17.
The lower electrode 11 may be electrically connected to a predetermined region of the semiconductor substrate 1. Therefore, the lower electrode 11 may be formed to have a wider width than the digit line 5. That is to say, the lower electrode 11 may have an extension A that does not overlap with the digit line 5. The extension A is electrically connected to a predetermined region of the semiconductor substrate 1 through a lower electrode plug 9 that penetrates the first and second interlayer insulating layers 3 and 7.
An MRAM cell using a vertical magnetic filed is described in U.S. Patent Application Publication No. US 2002/0036917 A1 to Nishimura et al., entitled Nonvolatile Solid-State Memory Devices and Memory Using Magnetoresistive Effect, and Recording/Reproducing Method of the Memory Device and Memory, published Mar. 28, 2002. As described in the abstract of this published patent application, a memory device is characterized by including a magnetoresistive element, a bit line formed above this magnetoresistive element, and a write line. The magnetoresistive element is formed immediately above the drain region of a field effect transistor.
FIGS. 2 and 3 are cross-sectional views illustrating MRAM cells disclosed in U.S. Patent Application Publication No. US 2002/0036917 A1.
Referring to FIG. 2, a lower interlayer insulating layer 23 is stacked on a semiconductor substrate 21. A magnetic resistor 30 is disposed on the lower interlayer insulating layer 23. The magnetic resistor 30 includes a lower electrode 25, an MTJ 27 and an upper electrode 29 which are sequentially stacked. In addition, the magnetic resistor 30 includes ferromagnetic layers having magnetic spins arrayed in the vertical direction. First and second digit lines 31a and 31b are disposed on both ends of the magnetic resistor 30. A bit line 35 is disposed to cross over the digit lines 31a and 31b. The bit line 35 is electrically connected to the upper electrode 29 through a bit line contact plug 33 that penetrates a predetermined region between the first and second digit lines 31a and 31b. 
A vertical magnetic field is used to magnetize the ferromagnetic layers of the magnetic resistor 30. The vertical magnetic field can be induced by a current that passes through the digit lines 31a and 31b. In this case, the current passing through the first digit line 31a should be anti-parallel to the current passing through the second digit line 31b. In addition, an overlap width B between the digit lines 31a and 31b and the magnetic resistor 30 may be reduced in order to improve magnetization efficiency of the magnetic resistor 30.
Referring to FIG. 3, an interlayer insulating layer 43 is stacked on a semiconductor substrate 41. A pair of digit lines 45a and 45b is disposed in the interlayer insulating layer 43. A magnetic resistor 54 is disposed on the interlayer insulating layer 43 between the digit lines 45a and 45b. The magnetic resistor 54 includes a lower electrode 49, an MTJ 51 and an upper electrode 53 which are sequentially stacked. The lower electrode 49 is electrically connected to a predetermined region of the semiconductor substrate 41 through a lower electrode contact plug 47 that penetrates the interlayer insulating layer 43 between the digit lines 45a and 45b. In addition, the upper electrode 53 is electrically connected to a bit line 55 that crosses over the magnetic resistor 54. The MRAM cell shown in FIG. 3 also employs ferromagnetic layers having magnetic spins, which are arrayed in the vertical direction.